The present invention relates to semiconductor device manufacturing techniques, and more specifically, to the formation of macros as layouts to monitor a bump formed at the junction of an n-type area and p-type area.
While the planar field effect transistor (FET) may appear to have reached the end of its scalable lifespan, the semiconductor industry has found an alternative approach with FinFETs. FinFET technology is viewed by many as the best choice for next generation advanced processes.
With advanced geometry planar FET technologies, such as 20 nanometer (nm), the source and the drain encroach into the channel, making it easier for leakage current to flow between them and in turn making it very difficult to turn the transistor off completely. FinFETs are three-dimensional structures that rise above the substrate and resemble a fin, hence the name. Certain techniques are utilized to form the fins for n-channel FETs and p-channel FETs.